The present invention relates generally to a method for metallizing deep vias in an insulative layer surface.
In the manufacture of semiconductor devices, metal conductive layers are patterned for the purpose of making interconnections between different points on the device. After formation of this patterned metal conductive layer, an electrically insulative material such as silicon dioxide or silicon nitride is deposited over the metal conductive layer by conventional deposition techniques. The surface of this electrically insulative layer will routinely be uneven due to the uneven underlying contour of the patterned conductive layer. The presence of a metal interconnective path beneath the insulative layer results in a corresponding elevated path in the surface contour of the insulative layer.
Often it is necessary, especially in high density devices, to form additional patterned conductive layers on the surface of the uneven insulative layer. In order to interconnect the metal conductive layers to each other and to the substrate, the generally followed practice is to etch holes in the insulative layer prior to deposition of a metallic layer onto the insulative layer. These holes or vias are located in positions where contacts are desired between conductive regions such as previously deposited patterned metal layers or conductive substrate layers underlying the insulative layer and metal patterns deposited on the insulative layer. Vias are typically formed by applying a resist mask to the insulative layer. The resist mask contains openings where via holes are to be etched into the insulative layer. An etchant is then applied to the mask layer such that via holes are etched where openings occur in the etching mask. The etching mask is then removed from the surface of the insulative layer and a metal layer is deposited onto the insulative layer.
Presently, poor step coverage of the metal conductive layer into deep vias represents a severe restriction which limits multi-level interconnect technologies. Traditional deposition techniques often result in thinning of the conductive layer around the interior walls of the via and produce discontinuities between metal deposited in the bottom of the via and metal deposited on the surface of the insulative layer. Such thinning and discontinuities result in long-range reliability problems and reduced yields.
Prior art methods for reducing the severity of these deep via metallization problems include bevelling of via edges and increasing the thickness of deposited metal layers. However, bevelled edges on deep vias tend to decrease packing density and the thickness of the metal layer is limited due to capacitance and topography considerations. The deposition of thicker metal layers is also of limited use due to the occurrence of self-shadowing. Self-shadowing is a phenomenon occurring during deposition of thick metal layers whereby access to a via is effectively prevented by narrowing of the upper portion of the via adjacent the surface of the insulative layer prior to complete filling of the lower regions of the via. This phenomenon prevents metal from being deposited on the lower sidewall of deep vias.
It is therefore an object of the present invention to provide an improved method for metallizing deep vias.
It is another object of the invention to reduce step coverage problems through the provision of metal fillets.
These and other objects of the present invention are attained by the provision of a method comprising defining and etching vias through the insulative layer to an underlying conductive region, forming metal fillets in the corners of the deep vias, depositing a conformal metal layer, etching the metal layer until all metal has been removed from the substrate surface and depositing a second metal interconnect layer and defining the desired pattern.
Fillets can be formed by first depositing a metal etch stop layer if needed to prevent damage or etching of the underlying conductive region to which contact will be made. A partially conformal layer of interconnect metal is then deposited. The metal layer is etched anisotropically until all but the via sidewalls are clear of metal. The fillets on the sidewalls displace metal subsequently deposited on the side of the vias laterally toward the center of the via, thereby preventing severe self-shadowing and thus improving the step coverage of the metal into the via.
Larger vias can also be utilized due to the formation of fillets on the via sidewalls making the step into the via more gradual and thus more receptive to subsequent metallization steps.
In an alternative embodiment, the penultimate etching step is stopped before all metal is removed from the surface of the insulative layer, thus leaving a thin layer of metal on the insulative layer surface and in the bottom of the via. Since some deposited metals tend to exhibit enhanced electromigration resistance, this configuration improves the life time of the interconnect. Furthermore, where silicon is contacted in the bottom of the via, the thin metal layer remaining in the bottom of vias will also serve as a pitting or migration barrier.
Further objects, features, and advantages of the present invention will become more apparent from the following description when taken with the accompanying drawings which show, for purposes of illustration only, several embodiments in accordance with the present invention.